MATRIX SCHEDULER FOR INSTRUCTION QUEUE IN OOO PROCESSORS

Abstract

Multi-core architectures and multi-threaded programs dominate today's world. In this world, delivering the highest IPC is of the utmost importance. Many mobile devices, including desktops and servers, require high performance and minimal power consumption. This has led to the RISC architecture revolution, led by ARM with the first iPhone. Since then, both Moore's law and new architectures have contributed to ever-faster and more power-efficient chips. What once were in-order processors are now being replaced with out-of-order designs to improve the throughput of instructions at the same power. The instruction queue is one of the most power-hungry regions of an out-of-order processor. An instruction queue, in its essence, is an entity that dispatches instructions to the execution units as soon as their input data is ready. Most modern processors use a CAM (content-addressable-memory) to realize the instruction queue. In a traditional IQ using CAM, the source arguments are constantly checked every cycle to see if they are ready, and the instruction is dispatched if all of the instruction's source arguments are ready. This approach is inherently power-hungry. The matrix instruction queue is an alternative to the traditional IQ and avoids CAM. The techniques that can be used to compress the matrix IQ to run efficiently, as well as the details of the IPC of this compressed matrix IQ and its resource usage, are presented in this thesis.