Multi-valued LSI/VLSI logic design /

Abstract

The procedures and methods presented in this dissertation are completely general, systematic, and easy to apply to any m-valued (m (GREATERTHEQ) 2) combinational and sequential LSI/VLSI design.

In brief, this dissertation has made the following four major contributions: (1) developed a multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior (Sections 5.2 and 5.3); (2) described a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart (Sections 4.2 and 5.3); (3) introduced a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX (Section 4.5); (4) presented a hierarchical design of LSI/VLSI with built-in parallel testing capability (Chapter 7).

This research describes a procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits. This scheme uses Multi-Valued MUlti-pleXers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main circuit), provide a thorough functional checking of the network at any time. Because the network can be partitioned into nearly identical subnetworks (Basic-Modular-Networks or BMNs) which, in turn, can be further partitioned into nearly identical sub-subnetworks, the testing of the entire network may be conducted in such a manner that all the sub-subnetworks and subnetworks are tested simultaneously by the built-in test circuits.